A Novel Approach to built an Area Efficient Architecture for Block LDPC Codes

Low Density Parity Checker (LDPC) decoder requires large amount of memory access which leads to high energy consumption. The amount of achievable memory bypassing depends on the decoding orders of the layers. The proposed decoder was implemented in TSMC 0.18m CMOS process. Experimental results show that for a LDPC decoder targeting IEEE 802.11n specification, the amount of memory access values can be reduced by 12.9% to 19.3% compared with the state-of-the-art design. At the same time, 95.6% to 100% hardware utilization rate is achieved. The advantages of being able to test a variety of codes such those found in communications standards including Wireless LAN(IEEE 802.11n), WIMAX(IEEE 802.16e) and DVB-S2, on a single hardware platform will make the transition from theory to practice a much smoother one. The LDPC decoder design is flexible, it can accept a new code without any redesign , the only thing that changes is the ROM configuration. It has been tested, functionally verified and simulated with the MODELSIM tool by using VHDL code. Also the decoder has been show to operate correctly on larger codes and as performance demands increase, it has been show to scale up to larger design well. To understand, develop, the block of layers in LDPC decoder. It develops, implements and verifies in VHDL the correctly functioning LDPC decoder in VHDL implement and verify in VHDL code, a scheduling that allows the flexibility and as well as it configures by